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Languguage OS II Version 10-94 (Knowledge Media)(1994).ISO
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332src.arc
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RESETV.LST
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1990-05-02
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52KB
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876 lines
Motorola 68000 Family Assembler (1.0 ) Wed May 02 21:06:40 1990
abs. rel. LC obj. code source line
---- ---- ---- --------- -----------
1 1 0000 |
2 2 0000 |** Set checksum at "CHECKVAL" below! **
3 3 0000 |
4 4 0000 | TTL Reset Vector and Code Size
5 5 0000 | OPT P=68332
6 6 0000 |******************************************************************************
7 7 0000 |** Exported portion ***
8 8 0000 |*V****************************************************************************
9 9 0000 |*** ***
10 10 0000 |*** MODULE: ***
11 11 0000 |*** RESETV - This module contains the reset vector for the system. ***
12 12 0000 |*** It also includes a longword that contains the size of ***
13 13 0000 |*** the code segment in bytes and all of the user custom- ***
14 14 0000 |*** ization parameters. ***
15 15 0000 |*** ***
16 16 0000 |*** ENVIRONMENT: ***
17 17 0000 |*** MC68332 BCC EVM system ***
18 18 0000 |*** ***
19 19 0000 |*** LANGUAGE: ***
20 20 0000 |*** M68MASM for MS-DOS MC68332 assembly language relocatable module ***
21 21 0000 |*** ***
22 22 0000 |*** SUMMARY OF CONTENTS: ***
23 23 0000 |*** <will be linked to start at $60000 for BCC> ***
24 24 0000 |*** System reset vector. ***
25 25 0000 |*** Code segment size. ***
26 26 0000 |*** User customization parameters. ***
27 27 0000 |*** ***
28 28 0000 |*** NOTES: ***
29 29 0000 |*** 1. Source equivalent copy of 332Bug parameter area for Motorola ***
30 30 0000 |*** FREEWARE Bulletin Board System (BBS) to produce object ***
31 31 0000 |*** equivalent code. See REVISION HISTORY below for version nbr. ***
32 32 0000 |*** 2. This source code can be freely used at no cost/obligation, ***
33 33 0000 |*** i.e. it is PUBLIC DOMAIN software. Please report any errors/ ***
34 34 0000 |*** additions to the SYSOP of the Motorola FREEWARE BBS. ***
35 35 0000 |*** 3. Parameters which reference linker symbols (XREF/XDEF) will ***
36 36 0000 |*** not be defined until link time, so the obj. code listed here ***
37 37 0000 |*** will not match the actual EPROM code. ***
38 38 0000 |*** ***
39 39 0000 |*^****************************************************************************
40 40 0000 |*** INTERNAL PORTION OF THE MODULE HEADER ***
41 41 0000 |******************************************************************************
42 42 0000 |*** ***
43 43 0000 |*** REVISION HISTORY (add changes to the top): ***
44 44 0000 |*** ***
45 45 0000 |*** DATE AUTHOR CHANGES ***
46 46 0000 |*** ---------- --------------- ------------------------------------- ***
47 47 0000 |*** 01/16/90 Peter S. Gilmour Initial version port to MS_DOS based ***
48 48 0000 |*** M68MASM from original source code. ***
49 49 0000 |*** Compatible with 332Bug version 1.01. ***
50 50 0000 |*** 05/02/90 Peter S. Gilmour Compatible with 332Bug version 1.02. ***
51 51 0000 |*** ***
52 52 0000 |******************************************************************************
53 53 0000 |
54 54 0000 |*** ***
55 55 0000 |*** XDEFS: ***
56 56 0000 |*** ***
57 57 0000 | XDEF ORIGIN Start of program space
58 58 0000 | XDEF CODESIZE Size of program space in bytes
59 59 0000 | XDEF CHECKSUM Permit access by confidence test
60 60 0000 |* Old CSn base addr reg. values
61 61 0000 | XDEF .CSBAR0,.CSBAR1,.CSBAR2,.CSBAR3,.CSBAR4,.CSBAR5
62 62 0000 | XDEF .CSBAR6,.CSBAR7,.CSBAR8,.CSBAR9,.CSBAR10
63 63 0000 |* Old CSn base addr reg. values
64 64 0000 | XDEF .CSOR0,.CSOR1,.CSOR2,.CSOR3,.CSOR4,.CSOR5
65 65 0000 | XDEF .CSOR6,.CSOR7,.CSOR8,.CSOR9,.CSOR10
66 66 0000 |* Common CSBOOT values
67 67 0000 | XDEF .CSBARBT Old/new CSBOOT base addr reg. value
68 68 0000 | XDEF .CSORBT Old/new CSBOOT option reg. value
69 69 0000 |* New CSn base addr reg. values
70 70 0000 | XDEF CSBAR0$,CSBAR1$,CSBAR2$,CSBAR3$,CSBAR4$,CSBAR5$
71 71 0000 | XDEF CSBAR6$,CSBAR7$,CSBAR8$,CSBAR9$,CSBAR10$
72 72 0000 |* New CSn base addr reg. values
73 73 0000 | XDEF CSOR0$,CSOR1$,CSOR2$,CSOR3$,CSOR4$,CSOR5$
74 74 0000 | XDEF CSOR6$,CSOR7$,CSOR8$,CSOR9$,CSOR10$
75 75 0000 |
76 76 0000 | XDEF .RAMMCR RAM Config. Reg. value
77 77 0000 | XDEF .RAMBAR RAM Base Addr. Reg. value
78 78 0000 | XDEF .PICR Periodic interrupt control reg. value
79 79 0000 | XDEF .PITR Periodic interrupt timer reg. value
80 80 0000 | XDEF RB_SP Rom Auto Boot SP location in ROM
81 81 0000 | XDEF RB_PC Rom Auto Boot PC location in ROM
82 82 0000 | XDEF CONSCI Console default SCI parameter table
83 83 0000 | XDEF .PARMS SCI parameter definition
84 84 0000 | XDEF .BAUD SCI baud rate value
85 85 0000 | XDEF .PARITY SCI parity value
86 86 0000 | XDEF .DATA SCI nbr. data bits value
87 87 0000 | XDEF .STOP SCI nbr. stop bits value
88 88 0000 | XDEF .XON_ENB SCI XON/XOFF enable value
89 89 0000 | XDEF .XON SCI XON value
90 90 0000 | XDEF .XOFF SCI XOFF value
91 91 0000 | XDEF PWR_ON Start of Power on branch vectors
92 92 0000 | XDEF PWR_INI MCU init. Power on branch vector
93 93 0000 | XDEF PWR_TTL Sign on title Power on branch vector
94 94 0000 | XDEF PWR_TST Self-test Power on branch vector
95 95 0000 | XDEF PWR_GO System Go Power on branch vector
96 96 0000 | XDEF SYSPATCH System patch area
97 97 0000 | XDEF SIGNON Offset to system sign on message text
98 98 0000 |*** ***
99 99 0000 |*** XREFS: ***
100 100 0000 |*** ***
101 101 0000 | XREF CONFTST Confidence test entry point
102 102 0000 | XREF SYSINIT Start of program (system init.)
103 103 0000 | XREF INIT_CS MCU initialization (chip selects, etc.
104 104 0000 | XREF MEMPAGE 16 Megabyte page
105 105 0000 |*** ***
106 106 0000 |*** Local macros: ***
107 107 0000 |*** ***
108 108 0000 |VECTOR MACRO ! SETUP VECTOR SPACE
109 109 0000 |SECTD SET 0 ! DEFINE DATA SECTION
110 110 0000 |SECTP SET 8 ! DEFINE PROGRAM SECTION
111 111 0000 | SECTION SECTP ! PUT USER INTO PROG. SECTION
112 112 0000 | ENDM !
113 113 0000 |
114 114 0000 |***
115 115 0000 |*** Local equates:
116 116 0000 |***
117 117 0000 000D |CR EQU $0D ASCII carriage return
118 118 0000 000A |LF EQU $0A ASCII line feed
119 119 0000 0020 |SPACE EQU $20 ASCII space
120 120 0000 |
121 121 0000 |*
122 122 0000 |* For M68332 BCC and PFB.
123 123 0000 |*
124 124 0000 |* NOTE: Unused upper address lines are specified as 1's so ABSOLUTE SHORT
125 125 0000 |* addressing (sign extension) can be used.
126 126 0000 |*
127 127 0000 2700 |SR_VAL EQU $2700 status register initial value.
128 128 0000 |
129 129 0000 0000 |RAM_BASE EQU $0 BCC RAM base address
130 130 0001 0000 |RAM_SIZE EQU $10000 BCC RAM size (bytes)
131 131 0006 0000 |ROM1_BASE EQU $60000 BCC EPROM base address
132 132 0002 0000 |ROM1_SIZE EQU $20000 BCC EPROM size (bytes)
133 133 0004 0000 |IRAM_BASE EQU $40000
134 134 FFFF E800 |FPCP_BASE EQU $FFFFE800 PFB MC68881/MC6882 base address
135 135 0000 |* . (Floating Point Co-Processor)
136 136 FFFF FA00 |SIM EQU $FFFFFA00 BCC M68332 System Integration Module base addr
137 137 FFFF FB00 |RAMCR EQU $FFFFFB00 BCC M68332 RAM Control Module base address
138 138 FFFF F800 |AUTO_BASE EQU $FFFFF800 Autovector base address
139 139 0000 |
140 140 0000 0000 |LOCALRAM EQU RAM_BASE base of local RAM
141 141 0000 4000 |SYSRAMSZ EQU $00004000 size of local RAM (for system use)
142 142 0001 0000 |LCLRAMMX EQU RAM_SIZE max size of local RAM (for M68332 BCC)
143 143 0000 4000 |USRRAM EQU LOCALRAM+SYSRAMSZ base of user RAM
144 144 0000 C000 |USRRAMSZ EQU LCLRAMMX-SYSRAMSZ size of user RAM
145 145 0000 0000 |RAMSTART EQU LOCALRAM alias for base of local RAM
146 146 0000 |
147 147 0006 0000 |LOCALROM EQU ROM1_BASE base of local ROM (use PC rel refs!)
148 148 0001 0000 |LCLROMSZ EQU $00010000 size of local ROM used by 332Bug
149 149 0000 00FF |ROMUNPGM EQU $FF unprogrammed state of a byte of EPROM
150 150 0000 00FF |FILL.1 EQU ROMUNPGM fill value for 1 byte = BYTE
151 151 0000 FFFF |FILL.2 EQU FILL.1<<8+FILL.1 fill value for 2 bytes= WORD
152 152 FFFF FFFF |FILL.4 EQU FILL.2<<16+FILL.2 fill value for 4 bytes= LONG WORD
153 153 0000 |
154 154 0001 0000 |RAM2_BASE EQU LOCALRAM+LCLRAMMX Next RAM base address
155 155 0008 0000 |ROM2_BASE EQU ROM1_BASE+ROM1_SIZE Next ROM base address
156 156 0000 |
157 157 0000 0400 |VECTSIZ EQU $400 Vector table size
158 158 0000 1000 |USERLEN EQU $1000 user space reserved
159 159 0000 4000 |MEMINC EQU $4000 memory increment for 130's or EVM's
160 160 0000 2BFC |STKLEN EQU MEMINC-USERLEN-VECTSIZ-4 size of bug/diag stack + static vars
161 161 0000 |
162 162 0000 |*
163 163 0000 |* Interrupt levels & vectors
164 164 0000 |*
165 165 0000 0007 |ABORTLVL EQU 7 abort level
166 166 0000 001F |ABORTVEC EQU 31 abort vector
167 167 0000 0007 |ACFAILVL EQU 7 AC-Fail level
168 168 0000 0041 |ACFAILVC EQU 65 AC-Fail vector
169 169 0000 0006 |TIMERLVL EQU 6 timer level: M68332 periodic int. timer
170 170 0000 0042 |TIMERVEC EQU 66 timer vector
171 171 0000 |
172 172 0000 |*
173 173 0000 |* Setup Base Addresses:
174 174 0000 |* 1. A31-A24 must= 0 (MC68332 only uses A0-A23; rest are unused!)
175 175 0000 |* 2. A10-A0 must= 0 (for Base Address Register usage).
176 176 0000 |*
177 177 00FF F800 |ADDRMASK EQU $00FFF800 Address mask (24-bits, A10-A0= 0)
178 178 0000 0000 |RAM EQU RAM_BASE&ADDRMASK Setup Base Addresses
179 179 0006 0000 |ROM EQU ROM1_BASE&ADDRMASK Setup Base Addresses
180 180 0001 0000 |RAM2 EQU RAM2_BASE&ADDRMASK Setup Base Addresses
181 181 0008 0000 |ROM2 EQU ROM2_BASE&ADDRMASK Setup Base Addresses
182 182 00FF E800 |FPCP EQU FPCP_BASE&ADDRMASK Setup Base Addresses
183 183 0004 0000 |IRAM EQU IRAM_BASE&ADDRMASK Setup Base Addresses
184 184 00FF F800 |AVEC_7 EQU AUTO_BASE&ADDRMASK Setup Base Addresses
185 185 0000 |
186 186 0000 0000 |CSBAR_XX EQU $0000 Reset (unused) value for CSBARn
187 187 0000 0000 |CSOR_XX EQU $0000 Reset (unused) value for CSORn
188 188 0000 |
189 189 0000 |*
190 190 0000 |* Option Register Equates (CSORBT, CSORn):
191 191 0000 |*
192 192 0000 0000 |B2K EQU 0 2K block size
193 193 0000 0001 |B8K EQU 1 8K block size
194 194 0000 0002 |B16K EQU 2 16K block size
195 195 0000 0003 |B64K EQU 3 64K block size
196 196 0000 0004 |B128K EQU 4 128K block size
197 197 0000 0005 |B256K EQU 5 256K block size
198 198 0000 0006 |B512K EQU 6 512K block size
199 199 0000 0007 |B1M EQU 7 1MB block size
200 200 0000 0000 |ASYNC EQU $0000 Asynchronous mode
201 201 0000 8000 |SYNC EQU $8000 Synchronous mode
202 202 0000 4000 |CS_UPPB EQU 2*$2000 Upper byte
203 203 0000 2000 |CS_LOWB EQU 1*$2000 Lower byte
204 204 0000 6000 |CS_BOTHB EQU 3*$2000 Both bytes (upper or lower)
205 205 0000 0800 |CS_R EQU 1*$800 Read
206 206 0000 1000 |CS_W EQU 2*$800 Write
207 207 0000 1800 |CS_RW EQU 3*$800 Read or write
208 208 0000 0000 |CS_AS EQU 0*$400 Address Strobe (AS*)
209 209 0000 0400 |CS_DS EQU 1*$400 Data Strobe (DS*)
210 210 0000 000E |CS_FAST EQU 14 Fast termination DSACK*
211 211 0000 000F |CS_EXT EQU 15 External termination DSACK*
212 212 0000 0040 |CS_WAIT EQU 1*$40 Wait cycles for DSACK*
213 213 0000 0000 |CS_CSP EQU 0*$10 CPU space
214 214 0000 0010 |CS_USP EQU 1*$10 User space
215 215 0000 0020 |CS_SSP EQU 2*$10 Supervisor space
216 216 0000 0030 |CS_SUSP EQU 3*$10 Supervisor/User space
217 217 0000 0002 |CS_LVL EQU 1*$2 Interrupt priority level
218 218 0000 0001 |CS_AVEC EQU 1 Autovector enable
219 219 0000 |
220 220 0000 |
221 221 0000 |* Select value for checksum below:
222 222 0000 |* - place "*" in front of the one you DON'T want assembled
223 223 0000 |*
224 224 0000 |*CHECKVAL EQU FILL.2 Checksum value for debugging
225 225 0000 B930 |CHECKVAL EQU $B930 Checksum value for finished product
226 226 0000 |* . - must not be same as FILL.2!
227 227 0000 |* The actual value of the checksum word is not known at the time
228 228 0000 |* that this file is assembled or linked. However, an "intelligent"
229 229 0000 |* checksum method is used whereby the program tells the user what
230 230 0000 |* the checksum should be if the checksum hasn't been programmed yet!
231 231 0000 |* Make the change, re-make the program, and blow new EPROM.
232 232 0000 |*
233 233 0000 |* The checksum word consists of two bytes that are placed at offset
234 234 0000 |* locations $0E-0F in the Bug EPROM and is used during execution of
235 235 0000 |* the confidence check to validate the EPROM contents.
236 236 0000 |*
237 237 0000 |
238 238 0000 |********************************
239 239 0000 |** Configuration Parameters **
240 240 0000 |********************************
241 241 0000 |* DO NOT ALTER! Must match with user documentation!
242 242 0000 |*
243 243 0000 | VECTOR
244 1m 0000 0000 +SECTD SET 0 ! DEFINE DATA SECTION
245 2m 0000 0008 +SECTP SET 8 ! DEFINE PROGRAM SECTION
246 3m 0000 + SECTION SECTP ! PUT USER INTO PROG. SECTION
247 244 0000 |*
248 245 0000 0000 |ORIGIN EQU *
249 246 0000 0000 2FFC |PWR_SSP DC.L LOCALRAM+VECTSIZ+STKLEN Init. SSP = below user ram
250 247 0004 0000 0090 |PWR_PC DC.L PWR_ON Init. PC = power on branch vector
251 248 0008 |**
252 249 0008 0002 0000 |CODESIZE DC.L ROM1_SIZE Set Code Size (in bytes)
253 250 000C FFFF |CHECKALT DC.W FILL.2 -- reserved -- (alternate checksum)
254 251 000E B930 |CHECKSUM DC.W CHECKVAL Allocate space for checksum word
255 252 0010 |* . If CHECKVAL = FILL.2, then change
256 253 0010 |* . value of CHECKALT location!
257 254 0010 |
258 255 0010 |* NOTE: "/256" is used in the Chip Select Tables below to shift address bits
259 256 0010 |* A23-A11 to bit positions B15-B3 (23-15= 8 bits = 256) for use in the
260 257 0010 |* SIM Base Address Registers.
261 258 0010 |
262 259 0010 |* Old Chip Select Table: (Rev. A BCC + Rev. A PFB)
263 260 0010 |*
264 261 0010 0003 |.CSBAR0 DC.W RAM/256+B64K CS0 base & option register values
265 262 0012 5830 |.CSOR0 DC.W 0*CS_WAIT+CS_UPPB+CS_RW+CS_AS+CS_SUSP
266 263 0014 0003 |.CSBAR1 DC.W RAM/256+B64K CS1 base & option register values
267 264 0016 3830 |.CSOR1 DC.W 0*CS_WAIT+CS_LOWB+CS_RW+CS_AS+CS_SUSP
268 265 0018 0103 |.CSBAR2 DC.W RAM2/256+B64K CS2 base & option register values
269 266 001A 6870 |.CSOR2 DC.W 1*CS_WAIT+CS_BOTHB+CS_R+CS_AS+CS_SUSP
270 267 001C 0103 |.CSBAR3 DC.W RAM2/256+B64K CS3 base & option register values
271 268 001E 3030 |.CSOR3 DC.W 0*CS_WAIT+CS_LOWB+CS_W+CS_AS+CS_SUSP
272 269 0020 0804 |.CSBAR4 DC.W ROM2/256+B128K CS4 base & option register values
273 270 0022 5870 |.CSOR4 DC.W 1*CS_WAIT+CS_UPPB+CS_RW+CS_AS+CS_SUSP
274 271 0024 0804 |.CSBAR5 DC.W ROM2/256+B128K CS5 base & option register values
275 272 0026 3870 |.CSOR5 DC.W 1*CS_WAIT+CS_LOWB+CS_RW+CS_AS+CS_SUSP
276 273 0028 FFE8 |.CSBAR6 DC.W FPCP/256+B2K CS6 base & option register values
277 274 002A 783F |.CSOR6 DC.W CS_EXT+CS_BOTHB+CS_RW+CS_AS+CS_SUSP
278 275 002C 0000 |.CSBAR7 DC.W CSBAR_XX CS7 base & option register values
279 276 002E 0000 |.CSOR7 DC.W CSOR_XX . -- unused --
280 277 0030 FFF8 |.CSBAR8 DC.W AVEC_7/256 CS8 base & option register values
281 278 0032 680F |.CSOR8 DC.W 0*CS_WAIT+CS_BOTHB+CS_R+CS_AS+CS_CSP+7*CS_LVL+CS_AVEC
282 279 0034 0000 |.CSBAR9 DC.W CSBAR_XX CS9 base & option register values
283 280 0036 0000 |.CSOR9 DC.W CSOR_XX . -- unused --
284 281 0038 0103 |.CSBAR10 DC.W RAM2/256+B64K CS10 base & option register values
285 282 003A 5030 |.CSOR10 DC.W 0*CS_WAIT+CS_UPPB+CS_W+CS_AS+CS_SUSP
286 283 003C |
287 284 003C |* Common Chip Select Table: (Rev. A BCC + Rev. A PFB) & (Rev. B BCC + Rev. B PFB)
288 285 003C |*
289 286 003C 0604 |.CSBARBT DC.W ROM/256+B128K CSBOOT base & option register values
290 287 003E 68B0 |.CSORBT DC.W 2*CS_WAIT+CS_BOTHB+CS_R+CS_AS+CS_SUSP
291 288 0040 |* - "2*CS_WAIT" = 2 wait cycles = AMD 27C1024-205LC 200 ns EPROM
292 289 0040 |* This EPROM is 2 wait cycles because it is always enabled, whereas the
293 290 0040 |* EPROM on the platform board (PFB) must first be enabled so it requires
294 291 0040 |* 3 wait cycles!
295 292 0040 |
296 293 0040 |* New Chip Select Table: (Rev. B BCC + Rev. B PFB)
297 294 0040 |*
298 295 0040 0003 |CSBAR0$ DC.W RAM/256+B64K CS0 base & option register values
299 296 0042 503E |CSOR0$ DC.W CS_FAST+CS_UPPB+CS_W+CS_AS+CS_SUSP
300 297 0044 0003 |CSBAR1$ DC.W RAM/256+B64K CS1 base & option register values
301 298 0046 303E |CSOR1$ DC.W CS_FAST+CS_LOWB+CS_W+CS_AS+CS_SUSP
302 299 0048 0003 |CSBAR2$ DC.W RAM/256+B64K CS2 base & option register values
303 300 004A 683E |CSOR2$ DC.W CS_FAST+CS_BOTHB+CS_R+CS_AS+CS_SUSP
304 301 004C 0000 |CSBAR3$ DC.W CSBAR_XX CS3 base & option register values
305 302 004E 0000 |CSOR3$ DC.W CSOR_XX . -- unused --
306 303 0050 FFF8 |CSBAR4$ DC.W AVEC_7/256 CS4 base & option register values
307 304 0052 680F |CSOR4$ DC.W 0*CS_WAIT+CS_BOTHB+CS_R+CS_AS+CS_CSP+7*CS_LVL+CS_AVEC
308 305 0054 FFE8 |CSBAR5$ DC.W FPCP/256+B2K CS5 base & option register values
309 306 0056 783F |CSOR5$ DC.W CS_EXT+CS_BOTHB+CS_RW+CS_AS+CS_SUSP
310 307 0058 0804 |CSBAR6$ DC.W ROM2/256+B128K CS6 base & option register values
311 308 005A 38F0 |CSOR6$ DC.W 3*CS_WAIT+CS_LOWB+CS_RW+CS_AS+CS_SUSP
312 309 005C 0804 |CSBAR7$ DC.W ROM2/256+B128K CS7 base & option register values
313 310 005E 58F0 |CSOR7$ DC.W 3*CS_WAIT+CS_UPPB+CS_RW+CS_AS+CS_SUSP
314 311 0060 0103 |CSBAR8$ DC.W RAM2/256+B64K CS8 base & option register values
315 312 0062 6870 |CSOR8$ DC.W 1*CS_WAIT+CS_BOTHB+CS_R+CS_AS+CS_SUSP
316 313 0064 0103 |CSBAR9$ DC.W RAM2/256+B64K CS9 base & option register values
317 314 0066 3030 |CSOR9$ DC.W 0*CS_WAIT+CS_LOWB+CS_W+CS_AS+CS_SUSP
318 315 0068 0103 |CSBAR10$ DC.W RAM2/256+B64K CS10 base & option register values
319 316 006A 5030 |CSOR10$ DC.W 0*CS_WAIT+CS_UPPB+CS_W+CS_AS+CS_SUSP
320 317 006C |
321 318 006C FFFF FFFF | DCB.B 4,FILL.1 <reserved>
322 319 0070 |
323 320 0070 |* Standby RAM Module
324 321 0070 |*
325 322 0070 FFFF |.RAMMCR DC.W $FFFF RAM Config. Reg. value
326 323 0072 FFFF |.RAMBAR DC.W $FFFF RAM Base Addr. Reg. value
327 324 0074 |* NOTE: If Bit0 (RAMDS) of .RAMBAR is set, then Standby RAM Module is not
328 325 0074 |* programmed, otherwise these two values are read and placed in the
329 326 0074 |* corresponding registers to program it. This allows the user to
330 327 0074 |* easily change configurations.
331 328 0074 |
332 329 0074 |* Periodic Interrupt Timer
333 330 0074 |* - assumes 32.768 KHz clock
334 331 0074 |*
335 332 0074 0642 |.PICR DC.W TIMERLVL<<8+TIMERVEC Periodic int. control reg. value
336 333 0076 |* . Defines interrupt level & vector.
337 334 0076 0102 |.PITR DC.W $0102 Periodic int. timing reg. value
338 335 0078 |* . Defines SYSCALL "tick" = 125 msec
339 336 0078 |
340 337 0078 |* ROM Auto Boot Vectors
341 338 0078 FFFF FFFF |RB_SP DC.L FILL.4 Allocate space for ROM BOOT SP and PC.
342 339 007C FFFF FFFF |RB_PC DC.L FILL.4!1 . PC bit0= 1 disables ROM BOOT!
343 340 0000 0000 | IFNE 4-(RB_PC-RB_SP)
344 341 0080 | FAIL 469 ROM BOOT SP/PC not adjacent anymore!
345 342 0080 | ENDC
346 343 0080 |
347 344 0080 |* SCI Console Default Initialization Table (CONSCI)
348 345 0080 |*
349 346 0080 |CONSCI DS 0 * USE THIS FOR CONNECTION TO TERMINALS
350 347 0080 |*
351 348 0080 |******** Each bit set in '.PARMS' below enables the 7 parameters **********
352 349 0080 |******** that follow. DO NOT ALTER THE VALUE OF '.PARAMS' below! **********
353 350 0080 |*
354 351 0080 0000 1C0F |.PARMS DC.L $1C0F
355 352 0084 |*
356 353 0084 2580 |.BAUD DC.W 9600 Baud rate (in decimal)
357 354 0086 00 |.PARITY DC.B 0 Parity: $00= none, 'E'= even, 'O'= odd
358 355 0087 08 |.DATA DC.B 8 Nbr. data bits: 7 or 8
359 356 0088 01 |.STOP DC.B 1 Nbr. stop bits: 1 or 2
360 357 0089 FF |.XON_ENB DC.B $FF XON/XOFF enable:
361 358 008A |* . $FF= enabled, $00= disabled
362 359 008A 11 |.XON DC.B $11 XON char: ^Q = $11
363 360 008B 13 |.XOFF DC.B $13 XOFF char: ^S = $13
364 361 008C |*
365 362 008C |
366 363 008C FFFF FFFF | DCB.B 4,FILL.1 <reserved>
367 364 0090 |
368 365 0090 |* Power On Branch Vectors
369 366 0090 |* - There are no entry/exit restrictions for register usage here.
370 367 0090 |*
371 368 0090 |PWR_ON:
372 369 0090 60FF 0000 |PWR_INI BRA.L INIT_CS Initialize chip selects, etc. for 68332
372 0094 0000 |
373 370 0096 |* . - returns to PWR_TTL
374 371 0096 60FF 0000 |PWR_TTL BRA.L PWR_TST Print sign on message title.
374 009A 0004 |
375 372 009C |* . - returns to PWR_TST
376 373 009C |* NOTE: PWR_TTL is not enabled yet. Signon message actually gets printed
377 374 009C |* in SYSINIT routine via TRAP 15 calls! This may be changed in the
378 375 009C |* future so simple SCI routines w/o stack usage can print messages
379 376 009C |* until system has been verified (use address regs for return addrs).
380 377 009C |*
381 378 009C 60FF 0000 |PWR_TST BRA.L CONFTST Perform confidence tests.
381 00A0 0000 |
382 379 00A2 |* . - returns to PWR_GO
383 380 00A2 60FF 0000 |PWR_GO BRA.L SYSINIT Go start up the system.
383 00A6 0000 |
384 381 00A8 |* . - never returns
385 382 00A8 FFFF FFFF | DCB.W 4*3,FILL.2 Reserve space for 4 more BRA.L's (3 words each)
385 382 00AC FFFF FFFF |
386 383 0000 00C0 |PWR_END EQU *
387 384 00C0 |
388 385 00C0 |* System Patch Area
389 386 00C0 |*
390 387 00C0 FFFF FFFF |SYSPATCH DCB.B $B0,FILL.1 Reserve patch space ($170-* = $B0).
390 387 00C4 FFFF FFFF |
391 388 0170 |
392 389 0170 |* Sign On Message Test String
393 390 0170 |*
394 391 0170 |SIGNON DS.W 0
395 392 0170 8F | DC.B SIGN$2-SIGN$1 Set msg byte count
396 393 0171 0D0A 0A |SIGN$1 DC.B CR,LF,LF
397 394 0174 3333 3242 |SIGN$3 DC.B '332Bug Debugger/Diagnostics - Version 1.02'
397 394 0178 7567 2044 |
397 394 017C 6562 7567 |
397 394 0180 6765 722F |
397 394 0184 4469 6167 |
397 394 0188 6E6F 7374 |
397 394 018C 6963 7320 |
397 394 0190 2D20 5665 |
397 394 0194 7273 696F |
397 394 0198 6E20 2031 |
397 394 019C 2E30 32 |
398 395 0000 002B |SIGN1SZ EQU *-SIGN$3 # chars in line #1 = $2B= 43
399 396 019F 2020 2020 | DCB.B 36,SPACE Pad to end of line (79-43= 36)
399 396 01A3 2020 2020 |
400 397 01C3 0D0A | DC.B CR,LF
401 398 01C5 2028 4329 |SIGN$4 DC.B ' (C) Copyright 1989, 1990 by Motorola Inc.'
401 398 01C9 2043 6F70 |
401 398 01CD 7972 6967 |
401 398 01D1 6874 2031 |
401 398 01D5 3938 392C |
401 398 01D9 2031 3939 |
401 398 01DD 3020 6279 |
401 398 01E1 204D 6F74 |
401 398 01E5 6F72 6F6C |
401 398 01E9 6120 496E |
401 398 01ED 632E |
402 399 0000 002A |SIGN2SZ EQU *-SIGN$4 # chars in line #2 = $2A= 42
403 400 0000 0011 |SIGN3SZ EQU ($200-(SIGNON-ORIGIN))-(*-SIGNON) Extra space= $11 = 17
404 401 01EF 2020 2020 | DCB.B 17,SPACE Pad to end of sigon space
404 401 01F3 2020 2020 |
405 402 0000 0200 |SIGN$2 EQU *
406 403 0200 |
407 404 0000 0000 | IFNE $200-(*-ORIGIN)
408 405 0200 | FAIL 470 Param area must= $200 to match user documentation!
409 406 0200 | ENDC
410 407 0000 0000 | IFNE $08-(CODESIZE-ORIGIN)
411 408 0200 | FAIL 471 CODESIZE must= offset $08 to match user documentation!
412 409 0200 | ENDC
413 410 0000 0000 | IFNE $0E-(CHECKSUM-ORIGIN)
414 411 0200 | FAIL 472 CHECKSUM must= offset $0E to match user documentation!
415 412 0200 | ENDC
416 413 0000 0000 | IFNE $10-(.CSBAR0-ORIGIN)
417 414 0200 | FAIL 473 .CSBAR0 must= offset $10 to match user documentation!
418 415 0200 | ENDC
419 416 0000 0000 | IFNE $12-(.CSOR0-ORIGIN)
420 417 0200 | FAIL 474 .CSOR0 must= offset $12 to match user documentation!
421 418 0200 | ENDC
422 419 0000 0000 | IFNE $3C-(.CSBARBT-ORIGIN)
423 420 0200 | FAIL 475 .CSBARBT must= offset $3C to match user documentation!
424 421 0200 | ENDC
425 422 0000 0000 | IFNE $3E-(.CSORBT-ORIGIN)
426 423 0200 | FAIL 476 .CSORBT must= offset $3E to match user documentation!
427 424 0200 | ENDC
428 425 0000 0000 | IFNE $40-(CSBAR0$-ORIGIN)
429 426 0200 | FAIL 477 CSBAR0$ must= offset $40 to match user documentation!
430 427 0200 | ENDC
431 428 0000 0000 | IFNE $42-(CSOR0$-ORIGIN)
432 429 0200 | FAIL 478 CSOR0$ must= offset $42 to match user documentation!
433 430 0200 | ENDC
434 431 0000 0000 | IFNE $70-(.RAMMCR-ORIGIN)
435 432 0200 | FAIL 479 .RAMMCR must= offset $70 to match user documentation!
436 433 0200 | ENDC
437 434 0000 0000 | IFNE $72-(.RAMBAR-ORIGIN)
438 435 0200 | FAIL 480 .RAMBAR must= offset $72 to match user documentation!
439 436 0200 | ENDC
440 437 0000 0000 | IFNE $74-(.PICR-ORIGIN)
441 438 0200 | FAIL 481 .PICR must= offset $74 to match user documentation!
442 439 0200 | ENDC
443 440 0000 0000 | IFNE $76-(.PITR-ORIGIN)
444 441 0200 | FAIL 482 .PITR must= offset $76 to match user documentation!
445 442 0200 | ENDC
446 443 0000 0000 | IFNE $78-(RB_SP-ORIGIN)
447 444 0200 | FAIL 483 RB_SP must= offset $78 to match user documentation!
448 445 0200 | ENDC
449 446 0000 0000 | IFNE $7C-(RB_PC-ORIGIN)
450 447 0200 | FAIL 484 RB_PC must= offset $7C to match user documentation!
451 448 0200 | ENDC
452 449 0000 0000 | IFNE $80-(.PARMS-ORIGIN)
453 450 0200 | FAIL 485 .PARMS must= offset $80 to match user documentation!
454 451 0200 | ENDC
455 452 0000 0000 | IFNE $84-(.BAUD-ORIGIN)
456 453 0200 | FAIL 486 .BAUD must= offset $84 to match user documentation!
457 454 0200 | ENDC
458 455 0000 0000 | IFNE $86-(.PARITY-ORIGIN)
459 456 0200 | FAIL 487 .PARITY must= offset $86 to match user documentation!
460 457 0200 | ENDC
461 458 0000 0000 | IFNE $87-(.DATA-ORIGIN)
462 459 0200 | FAIL 488 .DATA must= offset $87 to match user documentation!
463 460 0200 | ENDC
464 461 0000 0000 | IFNE $88-(.STOP-ORIGIN)
465 462 0200 | FAIL 489 .STOP must= offset $88 to match user documentation!
466 463 0200 | ENDC
467 464 0000 0000 | IFNE $89-(.XON_ENB-ORIGIN)
468 465 0200 | FAIL 490 .XON_ENB must= offset $89 to match user documentation!
469 466 0200 | ENDC
470 467 0000 0000 | IFNE $8A-(.XON-ORIGIN)
471 468 0200 | FAIL 491 .XON must= offset $8A to match user documentation!
472 469 0200 | ENDC
473 470 0000 0000 | IFNE $8B-(.XOFF-ORIGIN)
474 471 0200 | FAIL 492 .XOFF must= offset $8B to match user documentation!
475 472 0200 | ENDC
476 473 0000 0000 | IFNE $90-(PWR_ON-ORIGIN)
477 474 0200 | FAIL 493 PWR_ON must= offset $90 to match user documentation!
478 475 0200 | ENDC
479 476 0000 0000 | IFNE $90-(PWR_INI-ORIGIN)
480 477 0200 | FAIL 494 PWR_INI must= offset $90 to match user documentation!
481 478 0200 | ENDC
482 479 0000 0000 | IFNE $96-(PWR_TTL-ORIGIN)
483 480 0200 | FAIL 495 PWR_TTL must= offset $96 to match user documentation!
484 481 0200 | ENDC
485 482 0000 0000 | IFNE $9C-(PWR_TST-ORIGIN)
486 483 0200 | FAIL 496 PWR_TST must= offset $9C to match user documentation!
487 484 0200 | ENDC
488 485 0000 0000 | IFNE $A2-(PWR_GO-ORIGIN)
489 486 0200 | FAIL 497 PWR_GO must= offset $A2 to match user documentation!
490 487 0200 | ENDC
491 488 0000 0000 | IFNE $C0-(SYSPATCH-ORIGIN)
492 489 0200 | FAIL 498 SYSPATCH must= $C0 to match user documentation!
493 490 0200 | ENDC
494 491 0000 0000 | IFNE $170-(SIGNON-ORIGIN)
495 492 0200 | FAIL 499 SIGNON must= $170 to match user documentation!
496 493 0200 | ENDC
497 494 0200 |
498 495 0200 | END
498 lines assembled
symbol table:
symbol name attrib. section value
----------- ------- ------- -----
ORIGIN .text 8 0x0
494 491 488 485 482 479 476 473 470 467
464 461 458 455 452 449 446 443 440 437
434 431 428 425 422 419 416 413 410 407
403 @248 @57
CODESIZE .text 8 0x8
410 @252 @58
CHECKSUM .text 8 0xe
413 @254 @59
.CSBAR0 .text 8 0x10
416 @264 @61
.CSBAR1 .text 8 0x14
@266 @61
.CSBAR2 .text 8 0x18
@268 @61
.CSBAR3 .text 8 0x1c
@270 @61
.CSBAR4 .text 8 0x20
@272 @61
.CSBAR5 .text 8 0x24
@274 @61
.CSBAR6 .text 8 0x28
@276 @62
.CSBAR7 .text 8 0x2c
@278 @62
.CSBAR8 .text 8 0x30
@280 @62
.CSBAR9 .text 8 0x34
@282 @62
.CSBAR10 .text 8 0x38
@284 @62
.CSOR0 .text 8 0x12
419 @265 @64
.CSOR1 .text 8 0x16
@267 @64
.CSOR2 .text 8 0x1a
@269 @64
.CSOR3 .text 8 0x1e
@271 @64
.CSOR4 .text 8 0x22
@273 @64
.CSOR5 .text 8 0x26
@275 @64
.CSOR6 .text 8 0x2a
@277 @65
.CSOR7 .text 8 0x2e
@279 @65
.CSOR8 .text 8 0x32
@281 @65
.CSOR9 .text 8 0x36
@283 @65
.CSOR10 .text 8 0x3a
@285 @65
.CSBARBT .text 8 0x3c
422 @289 @67
.CSORBT .text 8 0x3e
425 @290 @68
CSBAR0$ .text 8 0x40
428 @298 @70
CSBAR1$ .text 8 0x44
@300 @70
CSBAR2$ .text 8 0x48
@302 @70
CSBAR3$ .text 8 0x4c
@304 @70
CSBAR4$ .text 8 0x50
@306 @70
CSBAR5$ .text 8 0x54
@308 @70
CSBAR6$ .text 8 0x58
@310 @71
CSBAR7$ .text 8 0x5c
@312 @71
CSBAR8$ .text 8 0x60
@314 @71
CSBAR9$ .text 8 0x64
@316 @71
CSBAR10$ .text 8 0x68
@318 @71
CSOR0$ .text 8 0x42
431 @299 @73
CSOR1$ .text 8 0x46
@301 @73
CSOR2$ .text 8 0x4a
@303 @73
CSOR3$ .text 8 0x4e
@305 @73
CSOR4$ .text 8 0x52
@307 @73
CSOR5$ .text 8 0x56
@309 @73
CSOR6$ .text 8 0x5a
@311 @74
CSOR7$ .text 8 0x5e
@313 @74
CSOR8$ .text 8 0x62
@315 @74
CSOR9$ .text 8 0x66
@317 @74
CSOR10$ .text 8 0x6a
@319 @74
.RAMMCR .text 8 0x70
434 @325 @76
.RAMBAR .text 8 0x72
437 @326 @77
.PICR .text 8 0x74
440 @335 @78
.PITR .text 8 0x76
443 @337 @79
RB_SP .text 8 0x78
446 343 @341 @80
RB_PC .text 8 0x7c
449 343 @342 @81
CONSCI .text 8 0x80
@349 @82
.PARMS .text 8 0x80
452 @354 @83
.BAUD .text 8 0x84
455 @356 @84
.PARITY .text 8 0x86
458 @357 @85
.DATA .text 8 0x87
461 @358 @86
.STOP .text 8 0x88
464 @359 @87
.XON_ENB .text 8 0x89
467 @360 @88
.XON .text 8 0x8a
470 @362 @89
.XOFF .text 8 0x8b
473 @363 @90
PWR_ON .text 8 0x90
476 @371 250 @91
PWR_INI .text 8 0x90
479 @372 @92
PWR_TTL .text 8 0x96
482 @374 @93
PWR_TST .text 8 0x9c
485 @381 374 @94
PWR_GO .text 8 0xa2
488 @383 @95
SYSPATCH .text 8 0xc0
491 @390 @96
SIGNON .text 8 0x170
494 403 403 @394 @97
CONFTST xref
381 @101
SYSINIT xref
383 @102
INIT_CS xref
372 @103
MEMPAGE xref
@104
VECTOR macro
243
CR abs. 0xd
400 396 @117
LF abs. 0xa
400 396 396 @118
SPACE abs. 0x20
404 399 @119
SR_VAL abs. 0x2700
@127
RAM_BASE abs. 0x0
178 140 @129
RAM_SIZE abs. 0x10000
142 @130
ROM1_BASE abs. 0x60000
179 155 147 @131
ROM1_SIZE abs. 0x20000
252 155 @132
IRAM_BASE abs. 0x40000
183 @133
FPCP_BASE abs. 0xffffe800
182 @134
SIM abs. 0xfffffa00
@136
RAMCR abs. 0xfffffb00
@137
AUTO_BASE abs. 0xfffff800
184 @138
LOCALRAM abs. 0x0
249 154 145 143 @140
SYSRAMSZ abs. 0x4000
144 143 @141
LCLRAMMX abs. 0x10000
154 144 @142
USRRAM abs. 0x4000
@143
USRRAMSZ abs. 0xc000
@144
RAMSTART abs. 0x0
@145
LOCALROM abs. 0x60000
@147
LCLROMSZ abs. 0x10000
@148
ROMUNPGM abs. 0xff
150 @149
FILL.1 abs. 0xff
390 366 321 151 151 @150
FILL.2 abs. 0xffff
385 253 152 152 @151
FILL.4 abs. 0xffffffff
342 341 @152
RAM2_BASE abs. 0x10000
180 @154
ROM2_BASE abs. 0x80000
181 @155
VECTSIZ abs. 0x400
249 160 @157
USERLEN abs. 0x1000
160 @158
MEMINC abs. 0x4000
160 @159
STKLEN abs. 0x2bfc
249 @160
ABORTLVL abs. 0x7
@165
ABORTVEC abs. 0x1f
@166
ACFAILVL abs. 0x7
@167
ACFAILVC abs. 0x41
@168
TIMERLVL abs. 0x6
335 @169
TIMERVEC abs. 0x42
335 @170
ADDRMASK abs. 0xfff800
184 183 182 181 180 179 178 @177
RAM abs. 0x0
302 300 298 266 264 @178
ROM abs. 0x60000
289 @179
RAM2 abs. 0x10000
318 316 314 284 270 268 @180
ROM2 abs. 0x80000
312 310 274 272 @181
FPCP abs. 0xffe800
308 276 @182
IRAM abs. 0x40000
@183
AVEC_7 abs. 0xfff800
306 280 @184
CSBAR_XX abs. 0x0
304 282 278 @186
CSOR_XX abs. 0x0
305 283 279 @187
B2K abs. 0x0
308 276 @192
B8K abs. 0x1
@193
B16K abs. 0x2
@194
B64K abs. 0x3
318 316 314 302 300 298 284 270 268 266
264 @195
B128K abs. 0x4
312 310 289 274 272 @196
B256K abs. 0x5
@197
B512K abs. 0x6
@198
B1M abs. 0x7
@199
ASYNC abs. 0x0
@200
SYNC abs. 0x8000
@201
CS_UPPB abs. 0x4000
319 313 299 285 273 265 @202
CS_LOWB abs. 0x2000
317 311 301 275 271 267 @203
CS_BOTHB abs. 0x6000
315 309 307 303 290 281 277 269 @204
CS_R abs. 0x800
315 307 303 290 281 269 @205
CS_W abs. 0x1000
319 317 301 299 285 271 @206
CS_RW abs. 0x1800
313 311 309 277 275 273 267 265 @207
CS_AS abs. 0x0
319 317 315 313 311 309 307 303 301 299
290 285 281 277 275 273 271 269 267 265
@208
CS_DS abs. 0x400
@209
CS_FAST abs. 0xe
303 301 299 @210
CS_EXT abs. 0xf
309 277 @211
CS_WAIT abs. 0x40
319 317 315 313 311 307 290 285 281 275
273 271 269 267 265 @212
CS_CSP abs. 0x0
307 281 @213
CS_USP abs. 0x10
@214
CS_SSP abs. 0x20
@215
CS_SUSP abs. 0x30
319 317 315 313 311 309 303 301 299 290
285 277 275 273 271 269 267 265 @216
CS_LVL abs. 0x2
307 281 @217
CS_AVEC abs. 0x1
307 281 @218
CHECKVAL abs. 0xb930
254 @225
SECTD abs. 0x0
@244
SECTP abs. 0x8
246 @245
PWR_SSP .text 8 0x0
@249
PWR_PC .text 8 0x4
@250
CHECKALT .text 8 0xc
@253
PWR_END .text 8 0xc0
@386
SIGN$2 .text 8 0x200
@405 395
SIGN$1 .text 8 0x171
@396 395
SIGN$3 .text 8 0x174
398 @397
SIGN1SZ abs. 0x2b
@398
SIGN$4 .text 8 0x1c5
402 @401
SIGN2SZ abs. 0x2a
@402
SIGN3SZ abs. 0x11
@403
.text section 8
165 symbols